1. Field of the Invention
This disclosure relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having capacitors, and a method of forming the same.
2. Description of the Related Art
In semiconductor memory devices such as DRAM (Dynamic Random Access Memory) devices, the device characteristics of a unit cell that includes a capacitor is heavily influenced by the capacitance of the capacitor. Thus, efforts have been made to increase the capacitance of the capacitor. Such efforts have included increasing an effective area of the capacitor, providing a dielectric layer positioned between both electrodes of the capacitor to become thin film, and forming a dielectric layer using high dielectric material.
Among the above methods, increasing the effective area of capacitor is perhaps the easiest, since the existing dielectric layer remains intact and processes that are well-known in the art are used.
Methods of increasing an effective area of the capacitor may be generally categorized into methods of constructing a lower electrode of a capacitor in a three-dimensional structure such as a pin, cylinder, or trench, methods of growing a HSG (Hemi-Spherical Grain) on a lower electrode, and methods of increasing the height of the lower electrode.
When a critical dimension (CD) between lower electrodes must be ensured, methods of growing HSG may occasionally cause a bridge between lower electrodes when a HSG is detached. In other words, the HSG growing method is generally difficult to apply to semiconductor devices having stringent design rules. Hence, an increase of effective area of capacitor to increase a capacitance generally employs a method of three-dimensionally constructing a lower electrode and increasing height thereof.
In the meantime, as the demand for increasingly integrated semiconductor devices continues, higher capacitances and lower leakage current characteristics become a necessity. The current trend is therefore to replace semiconductor memory devices having capacitors with a polysilicon/dielectric layer/polysilicon structure with semiconductor memory devices having capacitors with a MIM (Metal-Insulator-Metal) structure.
When a material having a high dielectric constant, e.g., Ta2O5 or BST (BaSrTiO3), is used as a capacitor dielectric layer, it becomes difficult to use a capacitor electrode made of a conventional polysilicon layer. That is, leakage currents generated by tunneling occur when a thickness of the dielectric layer is reduced. Hence, when a high-dielectric layer or ferroelectric layer is used for the dielectric layer, metal matter having a very high work-function is used for the capacitor electrode material.
The practice of forming an upper electrode with metal has tended to simplify the capacitor forming process. Previously, forming a polysilicon upper electrode in a cell region resulted in increased resistance in a peripheral circuit region since the polysilicon layer functions as a resistance element. However, when the upper electrodes are made of metal, a lower resistance in the peripheral circuit region is typically the result.
Generally, when defects occur in an upper electrode formation process due to a process condition error, the defects may not be detected. This is especially true when upper electrodes are formed of metal, which, as explained above, decreases the resistance in the peripheral circuit region. In this case, an entire upper electrode pattern may not be enough to measure in detail a CD as compared with a conventional polysilicon pattern. Thus, even though an abnormal pattern may be generated, the abnormality may be not sensed, and this causes process defects.
FIG. 1 is a layout diagram illustrating the shape of an upper electrode of a capacitor in a cell region and a peripheral circuit region of a semiconductor memory device according to an example of the conventional art.
Referring to FIG. 1, a capacitor lower electrode (not shown) is formed in a cell region 12, and a metal capacitor upper electrode 10 is formed on the capacitor lower electrode, the capacitor upper electrode extending into a portion of a peripheral circuit region 14. The edges of the capacitor upper electrode 10 in the peripheral circuit region 14 are essentially straight lines, the edges having no variation or pattern. The edges of the capacitor upper electrode 10 protrude into the peripheral circuit region 14 to connect with a metal contact (element 16 of FIG. 2) that is formed in a subsequent process.
The shape of the metal capacitor upper electrode 10 is generally the same as a polysilicon upper electrode. But, as was explained above, the occurrence of a defect in the upper electrode pattern may go undetected because a resistance is not formed in the peripheral circuit region. Furthermore, the width of the portion of the upper electrode 10 that extends into the peripheral circuit region 14 may not be controlled appropriately.
FIG. 2 is an electron microscope photograph that illustrates a defect that may be caused by the upper electrode pattern of FIG. 1.
As shown in FIG. 2, a flow effect is generated on an upper electrode pattern in a peripheral circuit region 14, and upper electrodes 10 separated by the peripheral circuit region 14 therebetween are connected with each other.
In this case, in a subsequent metal contact forming process, a contact hole for a metal contact cannot be properly formed by the upper electrode, thus causing process defects.
Embodiments of the invention address these and other disadvantages of the conventional art.